Verilog and SystemVerilog Gotchas
Produktnummer:
1867ac893a3caf41df8bb8219ea059f7c4
| Autor: | Mills, Don Sutherland, Stuart |
|---|---|
| Themengebiete: | Hardware Potential RTL SystemVerilog Verilog digital design modeling programming verification |
| Veröffentlichungsdatum: | 26.06.2007 |
| EAN: | 9780387717142 |
| Sprache: | Englisch |
| Seitenzahl: | 218 |
| Produktart: | Gebunden |
| Verlag: | Springer US |
| Untertitel: | 101 Common Coding Errors and How to Avoid Them |
Produktinformationen "Verilog and SystemVerilog Gotchas"
This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize, and avoid, these common coding mistakes. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug them. This book is unique because while there are many books that teach the language, and a few that try to teach coding style, no other book addresses how to recognize and avoid coding errors with these languages.
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