Haben Sie Fragen? Einfach anrufen, wir helfen gerne: Tel. 089/210233-0
oder besuchen Sie unser Ladengeschäft in der Pacellistraße 5 (Maxburg) 80333 München
+++ Versandkostenfreie Lieferung innerhalb Deutschlands
Haben Sie Fragen? Tel. 089/210233-0

Formal Equivalence Checking and Design Debugging

192,59 €*

Sofort verfügbar, Lieferzeit: 1-3 Tage

Produktnummer: 185f2ba16e495d4f60a14c229f1cc6c0a1
Autor: Kwang-Ting (Tim) Cheng Shi-Yu Huang
Themengebiete: ASIC RTL algorithms circuit computer-aided design (CAD) debugging diagnosis integrated circuit logic mechanics
Veröffentlichungsdatum: 30.06.1998
EAN: 9780792381846
Sprache: Englisch
Seitenzahl: 229
Produktart: Gebunden
Verlag: Springer US
Produktinformationen "Formal Equivalence Checking and Design Debugging"
Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: `With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley

Sie möchten lieber vor Ort einkaufen?

Sie haben Fragen zu diesem oder anderen Produkten oder möchten einfach gerne analog im Laden stöbern? Wir sind gerne für Sie da und beraten Sie auch telefonisch.

Juristische Fachbuchhandlung
Georg Blendl

Parcellistraße 5 (Maxburg)
8033 München

Montag - Freitag: 8:15 -18 Uhr
Samstags geschlossen