A Pipelined Multi-Core Machine with Operating System Support
Produktnummer:
18d3e62788a7c9475c82a58c0954842064
| Autor: | Lutsyk, Petro Oberhauser, Jonas Paul, Wolfgang J. |
|---|---|
| Themengebiete: | Field Programmable Gate Array (FPGA) artificial intelligence computer hardware computer programming distributed computer systems distributed systems embedded systems formal logic microprocessor chips multi core |
| Veröffentlichungsdatum: | 10.05.2020 |
| EAN: | 9783030432423 |
| Sprache: | Englisch |
| Seitenzahl: | 628 |
| Produktart: | Kartoniert / Broschiert |
| Verlag: | Springer International Publishing |
| Untertitel: | Hardware Implementation and Correctness Proof |
Produktinformationen "A Pipelined Multi-Core Machine with Operating System Support"
This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:• MIPS instruction set architecture (ISA) for application and for system programming• cache coherent memory system• store buffers in front of the data caches• interrupts and exceptions • memory management units (MMUs)• pipelined processors: the classical five-stage pipeline is extended by two pipelinestages for address translation• local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)• I/O-interrupt controller and a disk
Sie möchten lieber vor Ort einkaufen?
Sie haben Fragen zu diesem oder anderen Produkten oder möchten einfach gerne analog im Laden stöbern? Wir sind gerne für Sie da und beraten Sie auch telefonisch.
Juristische Fachbuchhandlung
Georg Blendl
Parcellistraße 5 (Maxburg)
8033 München
Montag - Freitag: 8:15 -18 Uhr
Samstags geschlossen