Generating Hardware Assertion Checkers
Produktnummer:
18b8cd61cf2156408193314e5f917e3221
| Autor: | Boulé, Marc Zilic, Zeljko |
|---|---|
| Themengebiete: | Emulator Hardware assertion-based verification assertion checkers automata hardware verification integrated circuit silicon debugging verification |
| Veröffentlichungsdatum: | 03.07.2008 |
| EAN: | 9781402085857 |
| Sprache: | Englisch |
| Seitenzahl: | 280 |
| Produktart: | Gebunden |
| Verlag: | Springer Netherland |
| Untertitel: | For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring |
Produktinformationen "Generating Hardware Assertion Checkers"
Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity.This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement.
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