FPGA Hardware Design for 3D Depth Estimation Algorithms

Optical 3D image processing algorithms are being used in applications, such as automation, healthcare, computer vision and microscopic imaging. The recent advances in the computation platforms and optical sensors have led to the evolution of new depth estimation algorithms. They work on a large data set and can be used for the 3D reconstruction of the objects. These algorithms are highly computationally intensive, presenting a challenge due to their large execution times. Desktop GPU based solutions are expensive from the perspective of power consumption. This research presents an optimized hardware architecture and a principle design flow specifically devised for 3D image processing algorithms. The target 3D image processing algorithms are: deflectometry phase-shift and plenoptic depth estimation. The former is developed to inspect defects on reflecting surfaces. The latter captures the light-field that can be exploited to estimate the 3D depth of the scene. Additionally, a modified plenoptic depth estimation algorithm is presented in this study that works on a single frame recorded by the camera. This algorithm incorporates a large number of complex recursive operations, and requires a substantial amount of resources to compute results. In this research work, the proposed FPGA hardware architecture is realized and evaluated by using available design tools. Moreover, proposed principle hardware design flow is tested and validated using both target 3D image processing algorithms. The results have shown that the performance of the target algorithms is significantly improved from the perspective of execution time and thus the hardware design is suitable for 3D image processing algorithms.